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| Preliminary Document Title A64S06161A 16M(1M x 16bit) Normal mode & Page mode Static Random Access Memory Revision history Rev. No. 0.0 History Initial issue Issue Date March 28, 2005 Remark Preliminary (March, 2005, Version 0.0) 1 AMIC Technology, Corp. Preliminary A64S06161A MEMORY 16M(1M x 16bit) Normal mode & Page mode Static Random Access Memory DESCRIPTION The A64S06161A is a 16Mb high speed, low power Static Random Access Memory(SRAM) organized as 1,048,576 words by 16 bits and supports Page Mode. The A64S06161A is a Pseudo SRAM based on successfully proven DRAM CELL SRAM which was specifically developed for cost sensitive, low power computing and communication applications such as mobile cellular phone handsets, personal digital assistants and other battery-operated consumer products. FEATURES * Standard Asynchronous SRAM Interface and Page Mode * Organization : 1M x 16Bit * Power Supply Voltage : 2.7 ~ 3.3 V * Page Size : 4 words * Page Mode Access (tPAA) : 35ns * Data Retention Voltage : 2.4V * Tri-state Output and TTL Compatible PRODUCT FAMILY Product Family A64S06161A 1 2 3 Operating Temperature -40 ~ 85 4 5 6 Voltage 2.7 ~ 3.3 V Speed 70 ISB1 (Max) 100uA IccDR (Max) 100uA ICC1 (Max) 2.0mA Mode Page PIN DESCRIPTION A B C D E F G H /LB IO8 IO9 VSS VCC IO14 IO15 A18 /OE /UB IO10 IO11 IO12 IO13 A19 A8 A0 A3 A5 A17 VSS A14 A12 A9 A1 A4 A6 A7 A16 A15 A13 A10 FUNCTIONAL BLOCK DIAGRAM Ref. Cont. DC Generator Circuit Sense Amp. A2 /CS IO1 IO3 IO4 IO5 /WE A11 /PD Add. Input Buffer IO0 IO2 VCC VSS IO6 IO7 Control Logic NC Add. Input Buffer Column Address IO0 Data I/O Buffer IO7 Row Decoder Row Address Write Driver Memory Array 8192 rows 128 x 16 columns IO8 IO15 Column Decoder /CS /OE /WE /UB /LB Note : E3 pin ( VSS) can be remain as a NC Name /CS /OE /WE A0A19 IO0IO15 Function Chip Select Input Output Enable Input Write Enable Input Address Input Data Input / Output Name VCC VSS /UB /LB Function Power Ground Upper Byte (IO815) Lower Byte (IO07) (March, 2005, Version 0.0) 2 AMIC Technology, Corp. Preliminary PRODUCT LIST Part Name A64S06161A-70U Function 16M, 48-FBGA , 70 ns, 3.0V, -4085 A64S06161A ABSOLUTE MAXIMUM RATING Item Voltage on any pin relative to Vss Voltage on Vcc supply relative to Vss Power Dissipation Storage temperature Operating Temperature (Extended) Symbol VIN, VOUT VCC PD TSTG TA Ratings -0.2 to VCC+0.3 V -0.2 to 3.6 1.0 -55 to 150 -40 ~ 85 Unit V V W Note : Stresses greater than those listed under "ABSOLUTE MAXIMUM RATINGS" may cause permanent damage to the device. This is stress rating only and the functional operation of the device under these or any other conditions above those indicated in the operation of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect reliability. TRUTH TABLE /CS H X L L L L L L L L /PD H H H H H H H H H H /OE X X H H L L L X X X /WE X X H H H H H L L L /LB X H L X L H L L H L /UB X H X L H L L H L L I/O 0~7 High-Z High-Z High-Z High-Z Data Out High-Z Data Out Data In High-Z Data In I/O 8~15 High-Z High-Z High-Z High-Z High-Z Data Out Data Out High-Z Data In Data In MODE Deselected Deselected Output Disabled Output Disabled Lower Byte Read Upper Byte Read Word Read Lower Byte Write Upper Byte Write Word Write Power Standby Standby Active Active Active Active Active Active Active Active (March, 2005, Version 0.0) 3 AMIC Technology, Corp. Preliminary RECOMMENDED DC OPERATING CONDITIONS Parameter Supply Voltage (5) Ground Input High Voltage Input Low Voltage Symbol Vcc Vss VIH VIL Min 2.7 0 0.8*Vcc -0.2 3) 1) A64S06161A Typ 3.0 0 - Max 3.3 0 Vcc+0.2 2) 0.4 Unit V V V V Note : 1.TA = -40 to 85, otherwise specified. 2. Overshoot : Vcc + 1.0V in case of pulse width 20 ns. 3. Undershoot : -1.0V in case of pulse width 20 ns. 4. Overshoot and undershoot are sampled, not 100% tested. 5. Stable power supply required 100 us before device operation. CAPACITANCE (TA = 25 , f = 1.0MHz) Symbol CIN COUT Parameter Input Capacitance Output Capacitance Condition VIN =0V VIO =0V Max. 8 10 Unit pF pF Note : This parameter is sampled and not 100% tested DC AND OPERATING CHARACTERISTICS Parameter Input Leakage Current Output Leakage Current Symbol ILI ILO Icc1 Test Condition VIN = Vss to Vcc /CS = VIH, /UB=/LB= VIH or /OE=VIH or /WE=VIL, VIO=Vss to Vcc Cycle Time = 1 us, 100%duty, IIO=0mA, /CS 0.2V, VIN 0.2V or VIN Vcc-0.2V Cycle time=Min, IIO=0mA, 100% duty /CS = VIL,VIN=VIL or VIH /CS1 = VIL, CS2=VIH,Tpwc = min Page address cycling IOL = 2 mA IOH = -1 mA /CS=VIH, /UB=/LB= VIH, Other inputs = VIH or VIL /CS Vcc-0.2V, /UB=/LB Vcc-0.2V (/UB,/LB Controlled) Other inputs = 0 or Vcc 2.2 0.3 100 Min -1 -1 Typ Max 1 1 Unit uA uA 2.0 mA Icc2 20 mA Iccp Output Low Voltage Output High Voltage Standby Current(TTL) Standby Current(CMOS) VOL VOH ISB ISB1 10 0.4 mA V V mA uA (March, 2005, Version 0.0) 4 AMIC Technology, Corp. Preliminary A64S06161A Data Retention Electric Characteristic TA = -40 to 85 (Normal), unless otherwise specified Item Voltage for Data Retention Symbol VDR Test Condition /CS=/PD=VIHVcc-0.2V or /UB,/LBVcc-0.2V, VINVCC-0.2V or VINVSS + 0.2V Vcc=2.4V, /CS=/PD=VIHVcc-0.2V or /UB,/LBVcc-0.2V, VINVCC-0.2V or VINVSS + 0.2V Refer to data retention wave form 0 tRC Min 2.4 Typ. (1) Max 3.3 Unit V Data Retention Current IccDR 100 uA Chip Deselect to Data Retention Time Operating Recovery Time (1) Vcc = 2.4V, TA = 25 tCDR tR - ns ns Data Retention Wave Form Data Retention Mode VCC 2.7V VIH VDR /CS Vcc-0.2V /CS VSS tCDR tR (March, 2005, Version 0.0) 5 AMIC Technology, Corp. Preliminary A64S06161A AC TEST CONDITIONS TA = -40 to 85 (Normal), unless otherwise specified PARAMETER Input Pulse Level Input Rise and Fall Time Input and Output Timing Reference Level Output Load Value 0.4V to 2.2V 5ns 1.5V CL = 30pF + 1TTL Load AC TEST LOADS TTL CL(1) Note : (1) Including jig and scope capacitance POWER UP TIME At starting, maintain stable power for a minimum 100us with /CS = /PD = high. (March, 2005, Version 0.0) 6 AMIC Technology, Corp. Preliminary AC CHARACTERISTICS (Vcc = 2.7 ~ 3.3V, TA = -40 to 85) 70ns Parameter List Read Cycle Time Address Set-up Time Address Access Time Chip Select to Output R E A D Output Enable to Valid Output /UB,/LB Access Time Chip select to Low-Z Output /UB, /LB Enable to Low-Z Output Output Enable to Low-Z Output Chip Disable to High-Z Output /UB, /LB Disable to High-Z Output Output Disable to High-Z Output Output Hold from Address Change Page Read Precharge Time Page Read Cycle Time Page Read Address Access Time Write Cycle Time Chip Select to End of Write W R I T E Address Valid to End of Write /UB, /LB Valid to End of Write Write Pulse Width Write Recovery Time Write to Output High-Z Data to Write Time Overlap Data Hold from Write Time End of Write to Output Low-Z Page Write Precharge Time Page Write Cycle Time Page Write Data to Write Time overlap Page Write Data Hold from Write Time Symbol Min tRC tAS tAA tCO tOE tBA tLZ tBLZ tOLZ tHZ tBHZ tOHZ tOH tP tPRC tPAA tWC tCW tAW tBW tWP tWR tWHZ tDW tDH tOW tP tPWC tPDW tPDH 70 60 60 60 50 0 0 40 0 5 10 35 20 0 20 10 10 5 0 0 0 10 10 35 35 25 25 25 70 0 70 70 35 70 Max A64S06161A Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns (March, 2005, Version 0.0) 7 AMIC Technology, Corp. Preliminary A64S06161A TIMING DIAGRAMS READ CYCLE (/PD = /WE = VIH) tRC Address(A2 - A19) Page Address(A0 - A1) tAA tCO tAS /UB,/LB tLZ(2) tBA tP /CS tOE /OE tHZ(1,2) tOHZ(1) DATA OUT Note (READ CYCLE) : 1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels 2. At any given temperature and voltage condition, tHZ(max.) is less than tLZ(min.) both for a given device and from device to device. 3. /WE is high for the read cycle. 4. Do not access device with cycle timing shorter than tRC for continuous periods > 16us. (March, 2005, Version 0.0) 8 AMIC Technology, Corp. Preliminary A64S06161A PAGE READ CYCLE (/PD = /WE = VIH) tRC Address (A2-A19) tPRC Page Corresponding (A0-A1) Addresses tAA /CS tAS /UB,/LB tCO tLZ(2) tBA tPAA tP(5) /OE tOE tHZ(1,2) tOHZ(1) DATA OUT Note (PAGE MODE READ CYCLE) : 1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels 2. At any given temperature and voltage condition, tHZ(max.) is less than tLZ(min.) both for a given device and from device to device. 3. /WE is high for the read cycle. 4. Do not access device with cycle timing shorter than tRC for continuous periods > 16us. 5. tP (precharge time) should be guaranteed for new Address. 6. After initial page access is accomplished, the page mode operation provides fast read access speed of random locations within that page (March, 2005, Version 0.0) 9 AMIC Technology, Corp. Preliminary WRITE CYCLE 1 (/CS Controlled, /PD = VIH) tWC ADDR tAS /CS tAW tBW /UB,/LB tWP /WE tDW Data In tDH tP tCW tWR A64S06161A High-Z Data Valid High-Z High-Z Data Out WRITE CYCLE 2 (/UB /LB Controlled, /PD = VIH) tWC ADDR tCW(2) /CS tAW tBW /UB,/LB tAS(3) /WE tDW Data In tDH tWP tP tWR(4) Data Valid High-Z Data Out Notes (WRITE CYCLE) : 1. A write occurs during the overlap of a low /CS and low /WE. A write begins at the latest transition among /CS going low and /WE going low: A write end at the earliest transition among /CS going high and /WE going high. tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the later of /CS going low to the end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR is applied in case a write ends as /CS. 5. Do not access device with cycle timing shorter than tRC for continuous periods > 16us. (March, 2005, Version 0.0) 10 AMIC Technology, Corp. Preliminary PAGE MODE WRITE CYCLE (/PD = VIH) A64S06161A tWC Address(A2 - A19) tPWC Page Address(A0 - A1) tP /CS tCW(3) tAS(1) tBW /UB,/LB tWP(1) /WE tDW DATA IN tDH tPDW tPDH tPDW tPDH DATA OUT High-Z Notes (PAGE MODE WRITE CYCLE) : 1. A write occurs during the overlap of a low /CS and low /WE. A write begins at the latest transition among /CS going low in initial page mode . A write end at the earliest transition among /CS going high and Page Address transition. tWP is measured from the beginning of write to the end of write in initial page access. 2. tPWC is measured from Page Address trasition (After initial page access) to Page Address transition or /CS going high. 2. tCW is measured from the later of /CS going low to the end of write in initial page access. 3. tAS is measured from the address valid to the beginning of write. 4. Do not access device with cycle timing shorter than tRC for continuous periods > 16us. 5. tP (precharge time) should be guaranteed for new Page Address. 6. After initial page access is accomplished, the page mode operation provides fast read access speed of random locations within that page (March, 2005, Version 0.0) 11 AMIC Technology, Corp. Preliminary A64S06161A Ordering Information Part No. A64S06161AG-70 A64S06161AG-70F A64S06161AG-70U A64S06161AG-70UF Access Time (ns) 70 70 70 70 Operating Current Max. (mA) 20 20 20 20 Package 48B Mini BGA 48B Pb-Free Mini BGA 48B Mini BGA 48B Pb-Free Mini BGA *Note : -U is for -40c ~ 85c temperature grade (March, 2005, Version 0.0) 12 AMIC Technology, Corp. Preliminary PACKAGE DIMENSION FOR BGA TYPE 48 BALL FINE PITCH 6mm x 8mm BGA(0.75mm ball pitch) Top View Bottom View B B B1 A64S06161A Unit: millimeters A1 INDEX MARK 6 B A 5 4 3 2 1 #A1 D C C1 B/2 A Y C C1 / 2 Side View E2 D C 0.90/Typ. Min A B B1 C C1 D E E1 E2 Y 5.90 7.90 0.30 0.20 - Typical 0.75 6.00 3.75 8.00 5.25 0.35 0.25 - Max 6.10 8.10 0.40 1.20 0.90 0.30 0.10 0.25/Typ. E E1 H G F E (March, 2005, Version 0.0) 13 AMIC Technology, Corp. C |
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